FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 163

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

WDT_CTRL
Default = 0x00 on
VCC POR, VTR
POR and HARD
RESET
NAME
Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
0xF4
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0
Bit[1] Reserved
Bit[2] Force Timeout, W
=1
Bit[3] P20 Force Timeout Enable, R/W
= 1
= 0
Note: The P20 signal will remain high for a minimum
of 1us and can remain high indefinitely. Therefore,
when P20 forced timeouts are enabled, a self-
clearing edge-detect circuit is used to generate a
signal which is ORed with the signal generated by
the Force Timeout Bit.
Bit[7:4] Reserved. Set to 0
WD timeout occurred
WD timer counting
Forces WD timeout event; this bit is self-
clearing
Allows rising edge of P20, from the
Keyboard Controller, to force the WD
timeout event.
still be forced by setting the Force Timeout
Bit, bit 2.
P20 activity does not generate the WD
timeout event.
163
DEFINITION
A WD timeout event may
STATE
C