FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 129

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

MLATCH Bit
VCC
MINT
new
D
Q
MINT
CLR
8042
RD 60
FIGURE 3 – MOUSE LATCH
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched
MINT (default), 1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched
KINT (default), 1=KINT is the latched 8042 KINT.
See the Configuration section for description on these registers.
Keyboard and Mouse PME Generation
The FDC37M81x sets the associated PME Status bits when the following conditions occur:
Active Edge on Keyboard Data Signal (KDAT)
Active Edge on Mouse Data Signal (MDAT)
These events can cause a PME to be generated if the associated PME Wake Enable register bit and
the global PME_EN bit are set. Refer to the PME Support section for more details on the PME
interface logic and refer to the Configuration section for details on the PME Status and Enable
registers.
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