MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 272

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Break (BRK) Module
19.4.1 Flag Protection During Break Interrupts
19.4.2 CPU During Break Interrupts
19.4.3 TIM1 and TIM2 During Break Interrupts
19.4.4 COP During Break Interrupts
19.5 Low-Power Modes
19.5.1 Wait Mode
Technical Data
272
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counters.
The COP is disabled during a break interrupt when BDCOP bit is set in
break auxiliary register (BRKAR).
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set. Clear the BW bit by writing logic 0 to it.
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
Break (BRK) Module
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA