HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 153

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.5
5.5.1
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared.
Figure 5.8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Internal
address bus
Internal
write signal
TGIEA
TGFA
TGI0A
interrupt signal
Usage Notes
Contention between Interrupt Generation and Disabling
φ
Figure 5.8 Contention between Interrupt Generation and Disabling
TIER0 write cycle by CPU
TIER0 address
Rev.4.00 Sep. 07, 2007 Page 123 of 1210
TGI0A exception handling
REJ09B0245-0400