HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 175

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 4—Reserved: Only 1 should be written to this bit.
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift toward the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM interface, these bits also select the row address
bits to be used for comparison.
Bit 3
MXC1
0
1
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
Bit 2
MXC0
0
1
0
1
Bit 0
RLW0
0
1
0
1
Description
8-bit shift
•
•
9-bit shift
•
•
10-bit shift
•
•
—
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
When 8-bit access space is designated: Row address bits A
A
When 16-bit access space is designated: Row address bits A
A
When 8-bit access space is designated: Row address bits A
A
When 16-bit access space is designated: Row address bits A
A
When 8-bit access space is designated: Row address bits A
A
When 16-bit access space is designated: Row address bits A
A
8
9
9
10
10
11
used for comparison
used for comparison
used for comparison
used for comparison
used for comparison
used for comparison
Rev.4.00 Sep. 07, 2007 Page 145 of 1210
REJ09B0245-0400
(Initial value)
(Initial value)
23
23
23
23
23
23
to
to
to
to
to
to