HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 221

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Usage Notes: When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In
the case of consecutive reads in different areas, for example, if the second access is a DRAM
access, only a T
6.34. However, in burst access in RAS down mode, the settings of these bits are enabled and an
idle cycle is inserted. The timing in this case is shown in figures 6.35 (a) and (b).
EXTAL
Address bus
RD
RAS
CAS, LCAS
Data bus
Figure 6.35 (a) Example of Idle Cycle Insertion in RAS Down Mode (ICIS1 = 1)
Address bus
RD
Data bus
p
φ
cycle is inserted, and a T
Figure 6.34 Example of DRAM Access after External Read
T
p
DRAM space read
T
r
T
T
c1
1
External read
T
T
c2
2
I
cycle is not. The timing in this case is shown in figure
T
T
3
I
External read
T
T
1
Rev.4.00 Sep. 07, 2007 Page 191 of 1210
p
DRAM space read
T
T
2
r
T
T
c1
3
Idle cycle
T
T
DRAM space read
c1
c2
REJ09B0245-0400
T
c1
T
c2