HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 176

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2.7
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock and controls the refresh timer.
DRAMCR is initialized to H'00 by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer.
Bit 7
RFSHE
0
1
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-
RAS refreshing.
Bit 6
RCW
0
1
Bit 5—Refresh Mode (RMODE): Selects whether self-refreshing is performed in software
standby mode.
Bit 5
RMODE
0
1
Rev.4.00 Sep. 07, 2007 Page 146 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
DRAM Control Register (DRAMCR)
:
:
Description
Refresh control is not performed
Refresh control is performed
Description
Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in Tr cycle
One wait state inserted in CAS-before-RAS refreshing
RAS falls in Tc1 cycle
Description
Self-refreshing is not performed in software standby mode
Self-refreshing is performed in software standby mode
RFSHE
R/W
7
0
RCW
R/W
6
0
RMODE
R/W
5
0
CMF
R/W
4
0
CMIE
R/W
0
3
CKS2
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0