HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 784

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE
0
1
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: This bit should be written with 0.
19.5.6
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 19.8. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Rev.4.00 Sep. 07, 2007 Page 754 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
RAM Emulation Register (RAMER)
Description
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
:
:
—
—
7
0
—
—
6
0
—
—
5
0
—
—
4
0
RAMS
R/W
0
3
RAM2
R/W
2
0
RAM1
R/W
1
0
(Initial value)
RAM0
R/W
0
0