PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 103

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

HDLC Channel 2 Receive Path Register
Value after reset: 00
SLIN(1-0)
LMOD(1-0)
HHR
Semiconductor Group
Select Line
00
01
10
11
Load Mode
00
XX
Host HDLC Receiver Access
0
1
H
Channel on DU (frame sync FSC, clock DCL or DCL/2)
Channel on DD (frame sync FSC, clock DCL or DCL/2)
Channel on SR (frame sync RFS, clock SCLK)
Channel on ST (frame sync TFS, clock SCLK)
When shift register contains one byte, it is loaded into HDLC
receiver as soon as possible (and, in addition, to DSP/host read
register for monitoring).
When shift register contains n bytes (XX = 01: n = 1; XX = 10:
n = 2; XX = 11: n = 4), the contents is loaded into DSP and host
read register, DSP or host (cf. HHR1 bit) write register is loaded
into HDLC receive buffer, and read DSP or host read register is
loaded into DSP or host write register (for software to be
accessed via a “Buffer Full” interrupt status).
DSP has access to modify HDLC receiver input (monitoring from
host still possible).
Host has access to modify HDLC receiver input (monitoring from
DSP still possible).
103
Read/Write
Register Description
Data Sheet 1998-07-01
Address 201F
PSB 7238
H