PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 80

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PSB7238

Manufacturer Part Number
PSB7238
Description
Joint Audio Decoder-Encoder - Multimode
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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Semiconductor Group
5
5.1
As explained in Section 3, the interrupt statuses are grouped on two interrupt lines, “high
priority” and “low priority” interrupts, respectively.
High Priority Interrupts (INTR)
FSC, RFS, TFS
BFUL1, BFUL2, BEMP1, BEMP2, BFHR1, BFHX1, BFHR2, BFHX2
Lower Priority Interrupts (INT)
T1, T2, T3
SAIN
HDLC1, HDLC2
DINT
GPI
MDR, MER, MDA, MEA, MAB, CIC1, CIC2
Corresponding interrupt status register exist for the internal DSP.
The interrupt status registers are physically separate for the host and for the DSP. Thus,
when an interrupt status is generated, the interrupt status bit is set in both registers.
The interrupt status disappears from the interrupt status register when the cause of the
interrupt status is removed by the software, or the interrupt is explicitly acknowledged.
Whenever possible, an interrupt status is made to disappear when the cause of that
interrupt status is removed (example: in/out audio data channel interrupts), in order to
spare the explicit writing of an acknowledge register address. In other cases the interrupt
statuses are explicitely acknowledged by writing a ‘1’ in a virtual acknowledge register.
The interrupt status bits have individual mask bits which have no influence on the setting
of the interrupt status bits, but only on the generation of the interrupt on the interrupt line.
When the mask bit is 0, the generation of the interrupt for the corresponding interrupt
status on line INTR or INT is prevented.
Register Description
Interrupt Structure
80
Register Description
Data Sheet 1998-07-01
PSB 7238

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