PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 58

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Note on Time-Slots of HDLC/Transparent Data Communication Controllers
If a time-slot is still active (either in receive or transmit direction) when a new frame sync
pulse is detected, the programmed length of the time-slot is not reduced but the time-slot
remains active until its end. However, the time-slot count logic for the new frame starts
immediately at the detection of the new frame sync pulse. A new time-slot can start
immediately after the currently active time-slot has been closed, thus permitting a
permanent reception or transmission (“time-slot length” = “distance between two
consecutive frame sync’s”).
The case where “time-slot length” > “distance between two consecutive frame sync’s”
should not occur.
Bit-Reversal Units
The bit-reversal units are working byte-based, i.e. when enabled via bits RMSB or XMSB
for receiver and transmitter, respectively, each byte inside the 32 bit data path is
reversed:
The bit-reversal unit is independent of the LMOD bits, but in case of LMOD = 00, 01, 10
not all bytes contain valid data.
When disabled (RMSB/XMSB = 0), the bit-reversal units are transparent.
Note on Latency of HDLC/Transparent Serial Data
When an HDLC receiver is enabled (via bit RAC), the HDLC receiver is clocked with the
serial interface clock even outside the selected time-slot. However, the logic at the input
of the HDLC receiver is only clocked with the serial clock during the selected time-slot.
Consequently, N bits are loaded into HRR register from the serial line after N clock edges
inside the selected time-slot (N is equal to 8, 16 or 32 depending on LMOD). Similarly,
data from HRW register is loaded into HDLC receiver only after a certain number of clock
edges inside the selected time-slot have occurred. The HDLC bit-engine works on serial
data, thus adding a delay of N clock cycles, but not necessarily inside the time-slot. The
latency (delay) of received data from the input pin to the HDLC FIFO is given in the
following as a function of LMOD (C
time-slot, C means the number of clock edges independent of the active time-slot):
31 30
24 25
25 24 23 22
30 31 16 17
TS
17 16 15 14
22 23 8
means the number of clock edges inside the active
58
9
9
14 15 0
8
7
Data Sheet 1998-07-01
Functional Blocks
6
1
PSB 7238
1
6
0
7