PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 113

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 17
Address
30A2
30A5
30A6
30AA
30AB
30AC
Receive FIFO
register while the other half is accessible to the controlling processor. The least
significant 5 bits of the address are not decoded for the FIFO access, thus always the
same address may be used to write to the FIFO. With the first write access the first byte
is written to the FIFO, with the second write access the second byte and so on. A random
access to the FIFO is not possible.
During the initialization phase the firmware does a re-programming on the following
registers of the HDLC1 controller to setup the default configuration for the
communication with a video-processor (see Section 6.2.3.3):
When read, register bits that are not in use (or reserved for future use) are not defined,
i.e. their value may be either ‘0’ or ‘1’.
The HDLC receive FIFO size is 2
receiver shift register while the second half is accessible to the controlling processor.
The least significant 5 bits of the address are not decoded for the FIFO access, thus
always the same address may be used to read out the FIFO contents. With the first read
access the first byte from the FIFO will be read, with the second read access the second
byte and so on. A random access to the FIFO contents is not possible.
Transmit FIFO
The transmit FIFO size is 2
Semiconductor Group
H
H
H
H
H
H
Data
80
40
83
0F
0F
50
H
H
H
H
H
H
RFIFO
XFIFO
Description
Transparent Mode
Receiver Reset
Power Up, MSB first for Receiver and Transmitter
Receiver: 16 bit time-slot
Transmitter: 16 bit time-slot
Interrupt Enable for RPF and XPR
32 bytes. One half is connected with the transmit shift
32 bytes. One half of the FIFO is connected to the
113
Read
Write
Register Description
Address 00-1F
Address 00-1F
Data Sheet 1998-07-01
PSB 7238
H
H