PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 47
PSB7238
Manufacturer Part Number
PSB7238
Description
Joint Audio Decoder-Encoder - Multimode
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.PSB7238.pdf
(190 pages)
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programmable baud rate generator (baud rate factor 1, 2, 3,
The wide range for the division factor for the CLKO output allows also for the possibility
to use it as a time marker (period on the order of 10 ms to synchronize another device
to the PSB 7238 time base).
When using the PLL (CM1 = 0), it is made sure that during reset phase CLKO delivers a
continuous 7.68 MHz clock. When using the non-PLL mode (CM1 = 1) CLKO goes low
while reset phase.
Timer T3 is derived from the DSP clock via a division by a programmable factor 1,
2
of hundreds of s to around a second.
Figure 18
Figure 17
CLKO and Timers
After reset the auxiliary clock output CLKO outputs a frequency of 7.68 MHz,
independent of the selection of CM1 bit. Alternatively, CLKO can be programmed (via
CKOS bit in register 2002
on INT1, as an optional synchronous time base for the DSP software.
Two timers T1 and T2 are provided, derived from the 8 kHz FSC (usually a
high-precision clock locked to the central clock of the synchronous network, e.g. ISDN)
with division factors (1, 2, 3,
Semiconductor Group
14
with a prescaler of 256. This generates an interrupt status and a maskable interrupt
H
) to output a frequency obtained from the DSP clock via a
, 64) and (1, 2, 3,
47
, 128), cascaded - yielding a time base
, 2
19
Data Sheet 1998-07-01
).
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