PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 88

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Description of Configuration and Control Registers
Unless otherwise indicated, all register bits are initialized to ‘0’ after a hardware reset.
When read, register bits that are not in use (or reserved for future use) are not defined,
i.e. their value may be either ‘0’ or ‘1’.
During the initialization phase the firmware does a re-programming on the following
registers of the configuration/control block to setup the default configuration for the
communication with a video-processor (see Section 6.2.3.3), i.e. the hardware reset
values given in the register description below are overwritten by the following values:
Address
2005
2006
2011
2012
2013
2017
2018
2019
201D
201E
Moreover, the firmware uses registers 2007
number of frame syncs.
The firmware also initialises the PLL Config registers 202C
values in case the PLL mode is selected via the CM1 pin. In case the non-PLL mode is
chosen, the firmware does not use these registers.
Chip Version Number Register
Value after reset: 30
VN(5-0)
H
H
H
H
H
H
H
H
H
H
Version Number of Chip
Data
04
1B
8F
10
42
AF
10
42
10
18
H
H
H
H
H
H
H
H
H
H
H
Description
SCLK is an output
SCLK Baud Rate = 34.56 MHz/28 = 1.23 MHz
Receive Uncompressed Audio: DU line, 16 bit linear
Position of first bit in time-slot: 32
Interrupt generated after 2 samples of 16 bits stored
Transmit Uncompressed Audio: DD line, 16 bit linear
Position of first bit in time-slot: 32
Interrupt generated after 2 samples of 16 bits stored
HDLC1 receiver connected to SR line
HDLC1 transmitter connected to ST line
88
H
and 2009
Read
H
for setting up the appropriate
H
and 202D
Register Description
Data Sheet 1998-07-01
H
to its appropriate
Address 2000
PSB 7238
H