PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 29

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CM1 = 0
CM1 = 1
the internal clock divided by a programmable baud rate factor (1, 2, 3,
generated.
When using the PLL (CM1 = 0), it is made sure that during reset phase CLKO delivers a
continuous 7.68 MHz clock. When using the non-PLL mode (CM1 = 1) CLKO goes low
while reset phase.
3.1.5
The chip internal clock is derived from a crystal connected across XTAL1,2 or from an
external clock input via pin XTAL1. Two different clock options are provided, controlled
by the clock mode pin CM1.
These clock modes are:
After reset the pin CLKO outputs a frequency of 7.68 MHz, independent of the selection
of CM1 bit. Alternatively, CLKO can be programmed to output the frequency of a
programmable divider (CKOS bit in register 2002
3.2
Note: The absolute addresses for the different internal register banks and memories are
Directly Accessible Register Bank (DARB)
The host accesses directly via its 8-bit address bus the so-called Directly Accessible
Register Bank (DARB) located between DSP addresses 3000
Semiconductor Group
given here and in the rest of this Data Sheet both as seen from the host and from
the embedded DSP, the latter information being included for the sake of
completeness only.
Clock Interface
Shared Memories
on XTAL1(,2). The internal frequency required is 34.56 MHz and is
obtained by providing a frequency of 7.68 MHz on XTAL1 input.
crystal, a 34.56 MHz crystal swinging at its basic harmonic has to be
connected to XTAL1,2.
The internal clock circuitry generates a frequency 4.5 times the input
The internal frequency is directly input via XTAL1(,2). When using a
29
Interfaces and Memory Organization
H
). Thus, a clock of frequency equal to
H
and 30FF
Data Sheet 1998-07-01
, 2
H
PSB 7238
.
19
) can be