PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 31

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

RC1, RC2, XC1, XC2, HR1, HR2, HX1, HX2 channel registers are located in the address
range 00
DSP. The register banks for the host and the DSP are physically separate from each
other. The read registers and write registers are physically separate.
The addresses for these registers are such that a 32-bit sample can be accessed from
the DSP via only two 16-bit read/write operations (16-bit data bus). From the host, the
access is byte-by-byte (8-bit data bus).
List of Registers
RC1:
RC2:
XC1:
XC2:
HRR1: 32-bit register for reading data from HDLC receiver 1 input shift register
HRW1: 32-bit register for writing data to be loaded into HDLC receiver 1 input
HXR1: 32-bit register for reading data from HDLC transmitter 1 output
HXW1: 32-bit register for writing data to HDLC transmitter 1 output shift register
HRR2: 32-bit register for reading data from HDLC receiver 2 input shift register
HRW2: 32-bit register for writing data to be loaded into HDLC receiver 2 input
HXR2: 32-bit register for reading data from HDLC transmitter 2 output
HXW2: 32-bit register for writing data to HDLC transmitter 2 output shift register
3.3
3.3.1
This area contains the locations for receiving/transmitting real-time audio and data
between the serial interfaces (IOM-2 and serial audio interface) and the host (or
embedded DSP).
The PSB 7238 implements two receive and two transmit audio channels, denoted RC1,2
and XC1,2 respectively. Further, two receive and two transmit channels are provided to
access the HDLC1,2 receiver input data and the HDLC1,2 transmitter output,
respectively, called HR1,2 and HX1,2.
Transfer of audio samples is interrupt supported, whereby two possibilities are provided:
– interrupt status generated after a programmable number of bits (1,
– interrupt indicating the start of a physical frame (normally at 8 kHz, either from FSC,
The interrupt statuses may generate a maskable interrupt on the high priority interrupt
lines INTR (Host) and/or INT0 (embedded DSP), respectively.
Semiconductor Group
shifted in/out;
RFS or TFS frame sync pulses): in this case the number of significant bits depends
on the time-slot length programmed for that channel on the line (DU/DD/SR/ST).
32-bit register for audio receive channel 1 (read)
32-bit register for audio receive channel 2 (read)
32-bit register for audio transmit channel 1 (write)
32-bit register for audio transmit channel 2 (write)
H
- 3F
Directly Accessible Register Bank
Input/Output Registers
H
for the host, and in the memory mapped area 3000
31
Interfaces and Memory Organization
Data Sheet 1998-07-01
H
, 32) have been
- 303F
PSB 7238
H
for the