PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 62

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
– CRC according to CCITT polynomial of order 16 or 32:
Programmable features for HDLC reception:
– CRC written in receive FIFO yes/no
– CRC according to CCITT polynomial of order 16 or 32 (common with transmitter).
Reception of back-to-back frames and consecutive frames with a shared flag, as well as
flags with shared ‘0’s is possible.
HDLC Frame Format
The HDLC transmitter starts an HDLC frame with a flag. It continues with the data from
the XFIFO (including the address). The end of a frame is indicated by a closing flag
preceded by the 16/32-bit CRC checksum or by an abort sequence. When no frame is
being transmitted inter-frame time-fill ‘1’ or “flags” is transmitted during the programmed
time-slot. Outside the selected time-slot, the output line is in “high impedance” state.
The HDLC receiver hunts for flags which are not followed by another flag or an abort
sequence. It stores the information - including the address field - in the RFIFO until the
end of the frame is detected. The status of the received frame (CRC status, end of frame
condition etc.) is reported via a status byte which is stored in the RFIFO immediately
following the last byte of the frame, and, simultaneously, in a register.
In Transparent Mode
In this mode, data is received and transmitted fully transparently without HDLC framing.
The received data is stored in the receive FIFO so that byte alignment in the FIFO
corresponds to byte alignment in the serial time-slot (if the length of the time-slot is a
multiple of 8 bits). Similarly, in transmit direction the byte alignment in the FIFO
corresponds to the time-slot boundaries in the transmit time-slot, if its length is a multiple
of 8 bits. When the transmit FIFO is empty, idle (‘1’) is transmitted during the active
time-slot. Outside the selected time-slot, the output line is in “high impedance” state.
CRC-16: x
(checksum: 1D0F
CRC-32: x
(checksum: C704DD7B
16
32
+ x
+ x
12
26
H
+ x
+ x
)
5
23
+ 1
H
+ x
)
22
+ x
16
+ x
12
+ x
62
11
+ x
10
+ x
8
+ x
7
+ x
5
Data Sheet 1998-07-01
+ x
Functional Blocks
4
+ x
2
PSB 7238
+ x + 1