AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 186

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

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Figure 18-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
1. Refer to
pin placement.
Pin
Configurations3,
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Receive)
UDR (Transmit)
UBRR[H:L]
(1)
Table 11-9 on page
UCSRB
73, and
SYNC LOGIC
GENERATOR
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
CLKio
Table 11-7 on page 71
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRC
7710D–AVR–08/09
for USART
XCK
TxD
RxD