AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 240

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

240
AT90PWM216/316
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See
Selection” on page 241
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see
Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 21-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADIF
ADCH
ADCL
ADSC
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
1
2
for details on differential conversion timing.
MUX and REFS
Update
2
3
MUX and REFS
Update
4
12
5
6
13
Sample & Hold
7
14
8
15
9
Sample & Hold
16
10
One Conversion
First Conversion
17
11
18
12
19
13
Conversion
Complete
14
20
“Changing Channel or Reference
15
21
16
22
Conversion
Complete
Sign and MSB of Result
23
LSB of Result
Next Conversion
1
24
Table
2
MUX and REFS
Update
25
3
21-1.
Sign and MSB of Result
7710D–AVR–08/09
Next
Conversion
1
LSB of Result
2
and REFS
Update
MUX
3