AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 34

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

7.6
7.6.1
34
PLL
AT90PWM216/316
Internal PLL for PSC
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency
clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of
PLL must be configurable by software. With a system clock of 8 MHz, the PLL output is 32Mhz
or 64Mhz.
The internal PLL in AT90PWM216/316 generates a clock frequency that is 64x multiplied from
nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC
Oscillator which is divided down to 1 MHz. See the
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register
will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC
Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency satu-
rates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be
noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1
MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only
when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is
set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep
modes
.
Table 7-7.
1.
2.
3.
RC Osc
Ext Osc
CKSEL
Ext Clk
0011
0101
0001
3..0
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
SUT1..0
Start-up Times when the PLL is selected as system clock
00
01
10
11
00
01
10
11
00
01
10
11
Start-up Time from Power-down
and Power-save
16K CK
16K CK
16K CK
6 CK
6 CK
6 CK
1K CK
1K CK
1K CK
1K CK
1K CK
(1)
(2)
(3)
Figure 7-4 on page
Reserved
Additional Delay from Reset
36.
14CK + 64 ms
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
(V
CC
14CK
14CK
14CK
14CK
= 5.0V)
7710D–AVR–08/09