AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 187

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

18.3
18.3.1
7710D–AVR–08/09
Clock Generation
Internal Clock Generation – Baud Rate Generator
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using synchronous mode.
Figure 18-2
Figure 18-2. USART Clock Generation Logic, Block Diagram
Signal description:
operation.
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (=
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
f
clk
io
), is loaded with the UBRR value each time the counter has counted down to zero or when
txn clk
rxn clk
xn cki
xn cko
f
clk
DDR_XCKn
XCKn
io
Pin
shows a block diagram of the clock generation logic.
xn cko
xn cki
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
System I/O Clock frequency.
clk
Down-Counter
io
Prescaling
Register
UBRRn
Sync
UBRRn+1
f
clk
UCPOLn
Detector
Edge
io
/2
f
Figure
clk
io
/(UBRR+1)). The Transmitter divides the
18-2.
/4
AT90PWM216/316
/2
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txn clk
rxn clk
187