WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 115

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
Select /RST duration
R3 (03h)
Unlock protected registers
R219 (DBh)
Alternate function and input/output selection for GPIO pins
R140 (8Ch)
R141 (8Dh)
R142 (8Eh)
R143 (8Fh)
R128 (80h)
R129 (81h)
R130 (82h)
R134 (86h)
R135 (87h)
Disable battery charger (only if battery type is not compatible with WM8351 charger)
R168 (A8h)
Re-lock protected registers
R219 (DBh)
Configure supply generation
R180 (B4h)
R181(B5h)
R183 (B7h)
R186 (BAh)
R187 (BBh)
R189 (BDh)
R190 (BEh)
R199 (C7h)
R200 (C8h)
R201 (C9h)
R203 (CAh)
R204 (CBh)
R206 (CEh)
R207 (CFh)
R209 (D1h)
R210 (D2h)
Proceed to startup and hand over to host processor
R6 (06h)
Table 64 Suggested Sequence of Register Writes for WM8351 Configuration in Development Mode
w
REGISTER
15
0
0
DEV_ADDR
GP11_FN
14
GP3_FN
GP7_FN
Note that configuration only includes registers that are required for starting up correctly. All other
register settings should be loaded after the WM8351 has started up.
Most of these control fields are described here within Section 14. See Section 11.6 for details of
Register Locking. See Section 20 for details of the GPIO configuration fields. See Section 17.7 for
details of the Battery Charger configuration.
When using the /RST signal to trigger configuration, writing to the _ENSLOT and RSTB_TO fields can
be omitted (the reset and power-up sequence has already taken place, so the write would have no
effect). However, additional writes to R13 or R176 should be added to enable the DC-DC converters
and LDO regulators one by one.
13
LDO1_ENSLOT[3:0]
LDO2_ENSLOT[3:0]
LDO3_ENSLOT[3:0]
LDO4_ENSLOT[3:0]
DC1_ENSLOT[3:0]
DC2_ENSLOT[3:0]
DC3_ENSLOT 3:0]
DC4_ENSLOT[3:0]
LS_ENSLOT[3:0]
GPn_DB (n = 0 to 12)
GPn_PU (n = 0 to 12)
GPn_PD (n = 0 to 12)
GPn_DIR (n = 0 to 12)
GPn_CFG (n = 0 to 12)
12
1
RSTB_TO
11
GP10_FN
10
GP2_FN
GP6_FN
9
8
FFFFh
0013h
7
6
GP1_FN
GP5_FN
GP9_FN
5
DC1_VSEL[6:0]
DC3_VSEL[6:0]
DC4_VSEL[6:0]
4
LDO1_VSEL[4:0]
LDO2_VSEL[4:0]
LDO3_VSEL[4:0]
LDO4_VSEL[4:0]
3
PD, April 2012, Rev 4.5
GP12_FN
GP0_FN
GP4_FN
GP8_FN
2
WM8351
1
0
115