WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 132

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
w
R183 (B7h)
DC-DC2
Control
Table 78 Hibernate Mode Control for DC-DC Converter 2
14.6.5
Each DC-DC Converter is monitored for voltage accuracy and fault conditions. An undervoltage
condition is set if the voltage falls below 95% of the required level. The action taken in response to a
fault condition can be set independently for each DC-DC Converter, as described in Table 79.
The DCn_ERRACT fields configure the fault response to disable the respective converter or to shut
down the entire system if desired. In addition, DC-DC Converter fault conditions also generate a
second-level interrupt (see Section 24).
To prevent false alarms during short current surges, faults are only signalled if the fault condition
persists. When a DC-DC Converter is started up, any initial fault condition is ignored until the
Converter has been allowed time to settle. The time for which any fault condition is ignored is set by
the PUTO register field, as described in Table 79.
R181 (B5h) for
DC-DC1
R184 (B8h) for
DC-DC2
R187 (BBh) for
DC-DC3
R190 (BEh) for
DC-DC4
R177 (B1h)
DCDC Active
options
Note: n is a number between 1 and 4 that identifies the individual DC-DC converter
Table 79 Fault Responses for DC-DC Converters
ADDRESS
ADDRESS
INTERRUPTS AND FAULT PROTECTION
15:14
13:12
BIT
9:8
12
BIT
DCn_ERRAC
T [1:0]
PUTO [1:0]
DC2_HIB_MO
DE
DC2_HIB_TRI
G [1:0]
LABEL
LABEL
DEFAULT
DEFAULT
00
00
00
0
Action to take on DC-DCn fault (as well
as generating an interrupt):
00 = ignore
01 = shut down converter
10 = shut down system
11 = reserved (shut down system)
Power up time out value for all
converters
00 = 0.5ms
01 = 2ms
10 = 32ms
11 = 256ms
DC-DC2 Hibernate behaviour:
0 = Continue as in Active state
1 = Disable converter output
DC-DC2 Hibernate signal select
00 = HIBERNATE register bit
01 = L_PWR1
10 = L_PWR2
11 = L_PWR3
Note that Hibernate is also selected
when a GPIO Hibernate input is
asserted.
DESCRIPTION
DESCRIPTION
PD, April 2012, Rev 4.5
Production Data
132