WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 155

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
17.5 EXTERNAL INTERRUPTS
17.6 BACKUP POWER
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The power supply control circuit has a first-level interrupt, EXT_INT (see Section 24). This comprises
three second-level interrupts which indicate if the USB, Wall or Battery supplies have been connected
or disconnected. Internal feedback signals USB_FB, WALL_FB and BATT_FB are used to indicate
when the associated supplies are present. Note that these interrupt events occur on both the rising
and falling edges of the trigger events. They can be masked by setting the applicable mask bits as
defined in Table 103.
R31 (1Fh)
Comparator
Interrupt Status
R39 (27h)
Comparator
Interrupt Status
Mask
Table 103 External Interrupts
A backup power source should be provided for the WM8351 on the VRTC pin. This can be a small
rechargeable battery or a high-capacitance capacitor (supercap). The purpose of this component is to
power the always-on functions such as the on-chip crystal oscillator, RTC and ALARM control
registers and UVLO comparator. As these circuit blocks store settings required for start-up, it is
desirable that they continue to operate even when no other power source is available.
The VRTC battery (or capacitor) maintains its charge from the Wall (LINE), USB or BATT sources.
The connection is illustrated in Figure 75. The series resistor limits the VRTC charge current. The 1F
capacitor is recommended also for stability; if this capacitor is too small or is not present, the VRTC
output may oscillate and cause a system reset.
Figure 75 Backup Power
ADDRESS
15:13
BIT
15
14
13
EXT_USB_FB_EINT
EXT_WALL_FB_EINT
EXT_BATT_FB_EINT
“IM_” + name of respective bit
in R31
LABEL
USB_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
WALL_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
BATT_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
DESCRIPTION
PD, April 2012, Rev 4.5
WM8351
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