WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 50

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
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The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the
register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK
frequency, and according to the selected mode of operation (Normal or USB). The applicable fields
are described in Table 9.
Selection of USB mode enables a 12MHz USB clock to be used to generate the required internal
clock signals. Table 10 describes the available sample rates using four different common MCLK
frequencies. The AIF_LRCLKRATE field must be set as described in Table 9.
In Normal mode, the programmable division set by ADC_CLKDIV must ensure that ADC_SYSCLK is
256 * ADC Sampling Frequency. DAC_CLKDIV must ensure that DAC_SYSCLK is 256 * DAC
Sampling Frequency.
In USB mode, ADC_CLKDIV must ensure that ADC_SYSCLK is 272 * ADC Sampling Frequency.
DAC_CLKDIV must ensure that DAC_SYSCLK is 272 * DAC Sampling Frequency.
Table 9 ADC / DAC Sample Rate Control
12.3.2
R48 (30h)
DAC
Control
R68 (44h)
ADC Clock
Control
R54 (36h)
DAC Clock
Control
REGISTER
ADDRESS
ADC / DAC SAMPLE RATES
BIT
2:0
2:0
12
AIF_LRCLKRATE
ADC_CLKDIV [2:0]
DAC_CLKDIV [2:0]
LABEL
DEFAULT
000
000
0
Mode Select
1 = USB mode (272 * Fs)
0 = Normal mode (256 * Fs)
ADC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
DAC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
DESCRIPTION
PD, April 2012, Rev 4.5
Production Data
50