WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 212

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
w
R100 (64h) Input Mixer Volume
R104 (68h) OUT1L Volume
R105 (69h) OUT1R Volume
R106 (6Ah) OUT2L Volume
R107 (6Bh) OUT2R Volume
R111 (6Fh) BEEP Volume
R112 (70h) AI Formating
R113 (71h) ADC DAC COMP
R76 (4Ch) Output Control
R77 (4Dh) Jack Detect
R92 (5Ch) OUT3 Mixer Control
R93 (5Dh) OUT4 Mixer Control
R74 (4Ah) Mic Bias Control
R78 (4Eh) Anti Pop Control
R80 (50h) Left Input Volume
R81 (51h) Right Input Volume
R88 (58h) Left Mixer Control
R89 (59h) Right Mixer Control
R96 (60h) Output Left Mixer Volume
R97 (61h) Output Right Mixer
R98 (62h) Input Mixer Volume L
R99 (63h) Input Mixer Volume R
REG
Volume
NAME
IN3R_TO_O
AIF_BCLK_I
MICB_ENA MICB_SEL
MIXOUTR_
OUT3_ENA
OUT4_ENA
OUT4_MIXI
OUT1L_EN
OUT1R_EN
OUT2L_EN
OUT2R_EN
MIXOUTL_
JDL_ENA
INR_ENA
INL_ENA
N_DST
UT2R
ENA
ENA
15
NV
0
0
0
0
A
A
A
A
0
IN3R_MIXOUTR_VOL[2:0]
IN3R_MIXINR_VOL[2:0]
OUT1L_MU
OUT1R_MU
OUT2L_MU
OUT2R_MU
INR_MUTE
INL_MUTE
JDR_ENA
14
TE
TE
TE
TE
0
0
0
0
0
0
0
0
0
0
0
0
OUT1R_ZC
OUT2R_ZC
OUT1L_ZC
OUT2L_ZC
INR_ZC
AIF_TRI
INL_ZC
13
0
0
0
0
0
0
0
0
0
0
0
0
0
DACR_TO_
DACR_TO_
DACR_TO_
AIF_LRCLK
MIXOUTR
MIXOUTL
OUT4
_INV
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT4_VRO
DACL_TO_
DACL_TO_
DACL_TO_
DACL_TO_
MIXOUTR
MIXOUTL
OUT3
OUT4
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
IN3L_MIXOUTL_VOL[2:0]
AIF_WL[1:0]
IN3L_MIXINL_VOL[2:0]
OUT3_VRO
OUT4_ATT
OUT2R_IN
10
N
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
OUT2_VRO
MIXINR_TO
OUT2R_IN
V_MUTE
_OUT4
9
ANTI_POP[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
AIF_FMT[1:0]
OUT1_VRO
MIXINL_TO
OUT1_VU
OUT1_VU
OUT2_VU
OUT2_VU
_OUT3
IN_VU
IN_VU
8
0
0
0
0
0
0
0
0
0
0
0
0
I
MIC_DET_
DAC_COM
ENA
DIS_OP_LN4[1:0]
7
0
0
0
0
0
0
0
0
0
P
INR_MIXOUTL_VOL[2:0]
INR_MIXOUTR_VOL[2:0]
IN2R_MIXINR_VOL[2:0]
IN3R_OUT2R_VOL[2:0]
DAC_COM
PMODE
6
0
0
0
0
0
0
0
0
0
0
ADC_COM
DIS_OP_LN3[1:0]
OUT1R_VOL[5:0]
OUT2R_VOL[5:0]
OUT1L_VOL[5:0]
OUT2L_VOL[5:0]
5
P
0
0
0
0
0
0
0
0
0
0
INR_VOL[5:0]
INL_VOL[5:0]
OUTPUT_D
RAIN_ENA
ADC_COM
PMODE
4
0
0
0
0
0
0
0
0
0
0
0
0
MCDTHR[2:0]
OUT4_TO_
IN3R_TO_
MIXOUTR
DIS_OP_OUT2[1:0]
OUT3
3
0
0
0
0
0
0
0
0
INL_MIXOUTR_VOL[2:0]
INL_MIXOUTL_VOL[2:0]
IN2L_MIXINL_VOL[2:0]
OUT4_MIXIN_VOL[2:0]
IN3L_TO_M
OUT3_TO_
OUT2_FB
IXOUTL
OUT4
2
0
0
0
0
0
0
0
INR_TO_MI
INR_TO_MI
MIXOUTR_
TO_OUT4
XOUTR
XOUTL
DIS_OP_OUT1[1:0]
MCDSCTHR[1:0]
1
0
0
0
0
0
0
0
0
0
0
0
0
0
PD, April 2012, Rev 4.5
INL_MIXINL
LOOPBACK
INL_TO_MI
INL_TO_MI
MIXOUTL_
MIXOUTL_
INR_MIXIN
TO_OUT3
TO_OUT4
OUT1_FB
XOUTR
XOUTL
R_VOL
_VOL
0
Production Data
0
0
0
0
0
0
0
0
0
0
0
0
DEFAULT
00E4h
00E4h
00E4h
02E4h
0A00h
0000h
0000h
0000h
0000h
0040h
0040h
0800h
1000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
212