WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 209

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
26 REGISTER MAP
26.1 OVERVIEW
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8351 can be configured using the Control Interface. All registers
not listed and all unused bits should be set to '0'.
Key to characters in brackets: K = protected by key, M = default in metal mask, R = read-only, W = write-only, O = read-only in ROM configs, D = protected by key in development mode, read-only
otherwise, n = never reset, p = reset by POR only, s = reset by state machine, sd = reset by state machine except in dev mode, u = reset on UVLO, m = reset on /MEMRST
w
R16 (10h) RTC Seconds/Minutes
R17 (11h) RTC Hours/Day
R10 (Ah) Power mgmt (3)
R11 (Bh) Power mgmt (4)
R12 (Ch) Power mgmt (5)
R13 (Dh) Power mgmt (6)
R14 (Eh) Power mgmt (7)
R0 (0h)
R1 (1h)
R2 (2h)
R3 (3h)
R4 (4h)
R5 (5h)
R6 (6h)
R8 (8h)
R9 (9h)
REG
Reset/ID
ID
Revision
System Control 1
System Control 2
System Hibernate
Interface Control
Power mgmt (1)
Power mgmt (2)
NAME
USB_SUSP
USE_DEV_
HIBERNAT
END_8MA
CHIP_ON
PINS (s)
LS_ENA
E (Ms)
(Ms)
CODEC_ISEL[1:0]
(Ms)
15
(M)
0
0
0
0
0
0
0
0
USB_SUSP
SYSCLK_E
SYS_RST
END (M)
DEV_ADDR[1:0] (s)
(KMs)
14
NA
CHIP_REV[3:0]
0
0
0
0
0
0
0
0
USB_MSTR
VBUF_ENA
ADC_HPF_
POWERCY
ENA
CLE
(Ms)
13
0
0
0
0
0
0
0
0
USB_MSTR
CODEC_EN
VCC_FAUL
CONFIG_D
T_OV (Ms)
_SRC (Ms)
ONE (s)
A (s)
12
0
0
0
0
0
0
0
0
0
RTC_MINS[6:0]
USB_MSTR
RECONFIG
RTC_TICK_
ENA (KMs)
LDO4_ENA
IN3R_ENA
FLL_ENA
_AT_ON
_500MA
RSTB_TO[1:0] (M)
(Ms)
(Ms)
11
CONF_STS[1:0]
0
0
0
0
0
0
OUTPUT_D
LDO3_ENA
USB_NOLI
RAIN_ENA
FLL_OSC_
OSC32K_E
IN3L_ENA
NA (KMs)
ENA
(Ms)
10
M
0
0
0
0
0
RTC_DAY[2:0]
USB_SLV_5
BG_SLEEP
LDO2_ENA
00MA (Ms)
CHG_ENA
AUTOINC
INR_ENA
(KMs)
(Ms)
(M)
9
(s)
0
0
0
0
0
0
0
SW_RESET/CHIP_ID[15:0] (n)
SW_VRTC_
TOCLK_EN
LDO1_ENA
MIC_DET_
INL_ENA
ENA (s)
ENA
(Ms)
8
0
0
0
0
0
0
0
A
0
IN3R_TO_O
WDOG_HIB
WDOG_HIB
MIXINR_EN
AUXADC_E
WDOG_DE
BUG (K)
_MODE
_MODE
NA (s)
UT2R
7
A
0
0
0
0
0
0
0
HIB_START
ET_ENA (s)
MIXINL_EN
CHIP_RES
UP_SEQ
6
0
0
0
A
0
0
0
0
0
0
WDOG_MODE[1:0] (KMs)
REG_RESE
OUT4_ENA OUT3_ENA
DACR_ENA DACL_ENA ADCR_ENA ADCL_ENA
MEM_VALI
T_HIB_MO
BIAS_ENA MICB_ENA
RTC_HPM
D (m)
DE
5
0
0
0
0
0
CHIP_SET_
RST_HIB_
MODE
4
MASK_REV[7:0]
UP
0
0
0
0
0
CUST_ID[7:0]
RTC_SECS[6:0]
IRQ_HIB_M
DCMP4_EN
ON_DEB_T
OUT2R_EN
DC4_ENA
SPI_CFG
ODE
(KM)
A (s)
(Ms)
3
(K)
0
0
0
A
0
RTC_HRS[4:0]
SPI_4WIRE
DCMP3_EN
HIB_MODE
VMID_ENA
OUT2L_EN
MEMRST_
DC3_ENA
(KM)
A (s)
(Ms)
2
0
0
A
0
WDOG_TO[2:0] (K)
HIB_MODE
SPI_3WIRE
OUT1R_EN
DCMP2_EN
PCCOMP_
MIXOUTR_
DC2_ENA
ON_POL
(KMs)
(KM)
A (s)
ENA
(Ms)
1
A
0
0
PD, April 2012, Rev 4.5
VMID[1:0]
DCMP1_EN
TEMPMON
_HIB_MOD
OUT1L_EN
MIXOUTL_
DC1_ENA
CS1_ENA
IRQ_POL
(Ms)
ENA
A (s)
(Ms)
0
(s)
E
0
A
0
WM8351
DEFAULT
1C02h
0004h
0204h
0214h
0204h
0000h
8A00h
0000h
0E00h
0000h
6143h
0000h
0001h
8000h
0000h
2000h
0000h
0000h
0100h
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