WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 211

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
w
R38 (26h) GPIO Interrupt Status
R39 (27h) Comparator Interrupt
R40 (28h) Clock Control 1
R41 (29h) Clock Control 2
R42 (2Ah) FLL Control 1
R43 (2Bh) FLL Control 2
R44 (2Ch) FLL Control 3
R45 (2Dh) FLL Control 4
R48 (30h) DAC Control
R50 (32h) DAC Digital Volume L
R51 (33h) DAC Digital Volume R
R53 (35h) DAC LR Rate
R54 (36h) DAC Clock Control
R58 (3Ah) DAC Mute
R59 (3Bh) DAC Mute Volume
R60 (3Ch) DAC Side
R64 (40h) ADC Control
R66 (42h) ADC Digital Volume L
R67 (43h) ADC Digital Volume R
R68 (44h) ADC Divider
R70 (46h) ADC LR Rate
R72 (48h) Input Control
R73 (49h) IN3 Input Control
REG
Mask
Status Mask
NAME
IM_EXT_US
DACR_ENA
ADCR_ENA
B_FB_EINT
TOCLK_EN
LRC_ADC_
DACL_ENA
ADC_HPF_
ADCL_ENA
IN3R_ENA IN3R_SHO
FLL_ENA
ENA
15
SEL
(s)
0
A
0
0
0
0
0
0
0
0
0
0
TOCLK_RA
DAC_MUTE
DAC_MUTE
IM_EXT_W
ALL_FB_EI
FLL_OSC_
MODE
NT (s)
ENA
14
RT
TE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL_RATIO[4:0]
IM_EXT_BA
DAC_MUTE
TT_FB_EIN
DAC_MON
ADC_TO_DACL[1:0]
RATE
T (s)
13
O
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_GP12_E
DAC_SB_FI
AIF_LRCLK
INT (s)
RATE
12
LT
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_GP11_E
IM_CODEC
_JCK_DET_
DACLRC_E
ADCLRC_E
MCLK_SEL
L_EINT (s)
ADC_TO_DACR[1:0]
INT (s)
11
NA
NA
0
1
0
0
0
0
0
0
0
0
0
0
0
0
_JCK_DET_
IM_GP10_E
IM_CODEC
R_EINT (s)
IN2R_ENA IN1RN_ENA IN1RP_ENA
ADCL_DAC_SVOL[3:0]
INT (s)
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL_OUTDIV[2:0]
IM_GP9_EI
IM_CODEC
_MICSCD_
EINT (s)
ADC_HPF_CUT[1:0]
NT (s)
9
0
0
0
0
0
0
0
0
0
0
0
0
0
_MICD_EIN
IM_GP8_EI
IM_CODEC
MCLK_DIV
DAC_VU
DAC_VU
ADC_VU
ADC_VU
NT (s)
T (s)
8
0
0
0
0
0
0
0
0
FLL_K[15:0]
FLL_REF_F
IM_GP7_EI
IN3L_ENA IN3L_SHOR
NT (s)
REQ
7
0
0
0
0
0
0
0
0
0
IM_GP6_EI
IM_WKUP_
OFF_STAT
E_EINT (s)
ADCR_DAC_SVOL[3:0]
FLL_RSP_RATE[3:0]
NT (s)
6
BCLK_DIV[3:0]
0
0
0
0
0
0
0
0
T
0
DACLRC_RATE[10:0]
ADCLRC_RATE[10:0]
HIB_STATE
IM_GP5_EI
IM_WKUP_
FLL_FRAC
_EINT (s)
NT (s)
5
0
0
0
0
0
0
0
0
DEEMP[1:0]
FLL_N[9:0]
IM_WKUP_
CONV_FAU
LT_EINT (s)
DACCLK_P
IM_GP4_EI
NT (s)
4
DACR_VOL[7:0]
OL
ADCR_VOL[7:0]
DACL_VOL[7:0]
ADCL_VOL[7:0]
0
0
0
0
0
0
0
0
DAC_SDMC
IM_GP3_EI
IM_WKUP_
WDOG_RS
ADCCLK_P
T_EINT (s)
LK_RATE
NT (s)
3
OL
0
0
0
0
0
0
0
0
0
0
0
IM_GP2_EI
IM_WKUP_
GP_PWR_
IN2L_ENA IN1LN_ENA IN1LP_ENA
ON_EINT
NT (s)
2
(s)
0
0
0
0
0
0
0
0
DAC_CLKDIV[2:0]
ADC_CLKDIV[2:0]
OPCLK_DIV[2:0]
FLL_RATE[2:0]
DACL_DATI
IM_WKUP_
ADCL_DATI
IM_GP1_EI
ONKEY_EI
NT (s)
NT (s)
FLL_CLK_SRC[1:0]
1
NV
NV
0
0
0
0
0
PD, April 2012, Rev 4.5
DACR_DAT
ADCR_DAT
IM_GP0_EI
IM_WKUP_
GP_WAKE
MCLK_DIR
UP_EINT
NT (s)
INV
INV
0
(s)
0
0
0
0
WM8351
DEFAULT
0000h
0040h
0000h
3A00h
C226h
0000h
00C0h
00C0h
8000h
00C0h
00C0h
0303h
0000h
7086h
0000h
0040h
0000h
4000h
0000h
0000h
0000h
0040h
0000h
211