WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 244

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
Register 28h Clock Control 1
Register 29h Clock Control 2
REGISTER
w
REGISTER
REGISTER
ADDRESS
ADDRESS
ADDRESS
FLL Control
R42 (2Ah)
R41 (29h)
Control 2
Clock
1
BIT
BIT
BIT
10:8
7:4
15
14
15
0
FLL_RSP_RATE[3:0]
LRC_ADC_SEL
FLL_OUTDIV[2:0]
FLL_OSC_ENA
MCLK_DIR
LABEL
LABEL
FLL_ENA
LABEL
DEFAULT
DEFAULT
DEFAULT
0
0
0000
010
0
0
Selects either ADCLRCLK or DACLRCLK to drive
LRCLK pin in Master mode
0 = DACLRCLK
1 = ADCLRCLK
Whether MCLK is an input or an output.
0 = MCLK is an input
1 = MCLK is an output
100 = SYSCLK / 5.5
101 = SYSCLK / 6
110 = Reserved
111 = Reserved
Digital Enable for FLL
0 = disabled
1 = enabled
Note that FLL_OSC_ENA must be enabled before
enabling FLL_ENA.
Analogue Enable for FLL
0 = FLL disabled
1 = FLL enabled
Note that FLL_OSC_ENA must be enabled before
enabling FLL_ENA.
FOUT clock divider
000 = FVCO / 2
001 = FVCO / 4
010 = FVCO / 8
011 = FVCO / 16
100 = FVCO / 32
101 = Reserved
110 = Reserved
111 = Reserved
FLL Loop Gain
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not changed from
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD, April 2012, Rev 4.5
REFER TO
REFER TO
REFER TO
Production Data
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