WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 196

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
23 WATCHDOG TIMER
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The WM8351 includes a watchdog timer designed to detect a possible software fault condition where
the host processor has locked up. The watchdog timer checks for any write operation to the watchdog
control register R4 (04h) or receipt of a heartbeat signal from the host processor on GPIO9 (see
Section 20). If neither event occurs within a programmable time, this is interpreted as a fault in the
host processor. The watchdog timer then raises an interrupt and/or generates a system reset; the
desired response to a watchdog timeout is set using the WDOG_MODE register field.
If GPIO9 is configured as HEARTBEAT input (GP9_FN = 0001, GP9_DIR = 1), then the Watchdog
Timer can only be reset by a rising logic level applied to the GPIO9 pin.
If GPIO9 is not configured as HEARTBEAT input, then the Watchdog Timer can only be reset by a
write operation to the watchdog control register R4 (04h).
If a System reset is triggered by the watchdog timeout, the WM8351 asserts the /RST pin and the
/RST and /MEMRST (GPIO) reset signals, resets the internal control registers and then initiates a
start-up sequence. If the watchdog timeout fault persists, then a maximum of 7 reset attempts will be
made. If the watchdog timeout occurs more than 7 times, the WM8351 will remain in the OFF state
until the next valid ON state transition event occurs.
The watchdog timer can be halted for debug purposes using the WDOG_DEBUG bit. The watchdog
can be disabled in Hibernate mode using the WDOG_HIB_MODE bit. The watchdog timer duration is
set using WDOG_TO, as described in Table 139.
The Watchdog timeout interrupt event is indicated by the SYS_WDOG_TO_EINT register field. This is
one of the second-level interrupts which triggers a first-level System Interrupt, SYS_INT (see
Section 24). This can be masked by setting the mask bit as described in Table 140.
R3 (03h)
System
control 1
R4 (04h)
System
control 2
R5 (05h)
System
Hibernate
Note: WDOG_HIB_MODE can be accessed through R4 or through R5. Reading from or writing to
either register location has the same effect.
Table 139 Controlling the Watchdog Timer
ADDRESS
BIT
5:4
2:0
7
7
7
WDOG_DEBU
G
WDOG_HIB_M
ODE
WDOG_MODE
[2:0]
WDOG_TO
[2:0]
WDOG_HIB_M
ODE
LABEL
on CONFIG
Dependant
DEFAULT
settings
101
0
0
0
Halts watchdog timer for system debugging
0 = normal operation
1 = WDOG halt
Watchdog behaviour in HIBERNATE state
0 = WDOG disabled in Hibernate
1 = WDOG controlled by WDOG_MODE in
Hibernate
Watchdog mode
00 = Disabled
01 = SYS_WDOG_TO interrupt on time-out
10 = WKUP_WDOG_RST interrupt and
System reset on time-out
11 = SYS_WDOG_TO interrupt on first time-
out, WKUP_WDOG_RST interrupt and
System reset on second time-out.
Protected by security key.
Watchdog timeout (seconds)
The timer is reset to this value when a
HEARTBEAT signal edge is detected or the
host writes to the watchdog control register.
000 = 0.125s
… (time doubles with each step)
101 = 4s
11x = Reserved
Protected by security key.
Watchdog behaviour in HIBERNATE state
0 = WDOG disabled in Hibernate
1 = WDOG controlled by WDOG_MODE in
Hibernate
DESCRIPTION
PD, April 2012, Rev 4.5
Production Data
196