WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 96
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WM8351CGEB/RV
Manufacturer Part Number
WM8351CGEB/RV
Description
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
1.WM8351CGEBRV.pdf
(330 pages)
- Current page: 96 of 330
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WM8351
13.11 COMPANDING
w
When the loopback feature is enabled, the audio ADC’s digital output data is looped back to the audio
DAC and converted back into an analogue signal. This is often useful for test and evaluation
purposes.
R113 (71h)
ADC Control
Table 47 Enabling loopback
The WM8351 supports A-law and -law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
Table 49 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out by
ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 + |x|) / ln( 1 + )
law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of
data.
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4-bits).
13.10.4 LOOPBACK
ADDRESS
R113 (71h)
Companding
Control
REGISTER
ADDRESS
BIT
0
BIT
4
5
6
7
LOOPBACK
ADC_COMPM
ODE
ADC_COMP
DAC_COMPM
ODE
DAC_COMP
LABEL
LABEL
-1 ≤ x ≤ 1
for x ≤ 1/A
for 1/A ≤ x ≤ 1
DEFAULT
DEFAULT
0
0
0
0
0
Digital Loopback Function
0 = No loopback.
1 = Loopback enabled, ADC data output is
fed directly into DAC data input.
ADC Companding mode select:
0 = µ-law
1 = A-law
(Note: Setting ADC_COMPMODE=1
selects 8-bit mode when DAC_COMP=0
and ADC_COMP=0)
ADC Companding enable
0 = off
1 = on
DAC Companding mode select:
0 = µ-law
1 = A-law
(Note: Setting DAC_COMPMODE=1
selects 8-bit mode when DAC_COMP=0
and ADC_COMP=0)
DAC Companding enable
0 = off
1 = on
DESCRIPTION
DESCRIPTION
PD, April 2012, Rev 4.5
Production Data
96
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