CS8427 Cirrus Logic, CS8427 Datasheet - Page 14

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

5.
A 3-wire serial audio input port and a 3-wire serial
audio output port is provided. Each port can be ad-
justed to suit the attached device by setting the con-
trol registers. The following parameters are
adjustable: master or slave, serial clock frequency,
audio data resolution, left or right justification of
the data relative to left/right clock, optional 1-bit
cell delay of the 1st data bit, the polarity of the bit
clock and the polarity of the left/right clock. By set-
ting the appropriate control bits, many formats are
possible.
Figure 17
mats, along with the control bit settings. The clock-
ing of the input section of the CS8427 may be
derived from the incoming ILRCK word rate clock,
using the on-chip PLL. The PLL operation is de-
scribed in
of use with the serial audio input port, the PLL
locks onto the leading edges of the ILRCK clock.
Figure 18
mats, along with the control bit settings. A special
AES3 direct output format is included, which al-
lows serial output port access to the V, U, and C
bits embedded in the serial audio data stream. The
14
THREE-WIRE SERIAL AUDIO
PORTS
shows a selection of common output for-
“AES3 Receiver” on page
shows a selection of common input for-
15. In the case
P bit is replaced by a bit indicating the location of
the Z preamble that marks the block start. This for-
mat is only available when the serial audio output
port is being clocked by the AES3 receiver recov-
ered clock.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the appropriate
clock domain master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be syn-
chronous to the appropriate master clock, but the
serial bit clock can function in asynchronous burst
mode if desired. By appropriate phasing of the
left/right clock and control of the serial clocks,
CS8427’s can be multiplexed to share one serial
port. The left/right clock should be continuous, but
the duty cycle does not have to be 50%, provided
that enough serial clocks are present in each phase
to clock all the data bits. When in slave mode, the
serial audio output port must not be set to right jus-
tified data.
When using the serial audio output port in slave
mode with an OLRCK input which is asynchro-
nous to the port’s data source, an interrupt bit
(OSLIP) is provided to indicate when repeated or
dropped samples occur.
CS8427
DS477PP3