CS8427 Cirrus Logic, CS8427 Datasheet - Page 41

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

DS477PP3
RERR
ILRCK
ISCLK
SDIN
TCBL
OSCLK
OLRCK
SDOUT
INT
U
OMCK
DGND
VL+
H/S
TXN
TXP
AD1/CDIN
SCL/CCLK
25
26
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
11
Receiver Error (Output) - When high, indicates an error condition from the AES3 receiver. The status of
this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go
high are: validity, parity error, bi-phase coding error, confidence, as well as loss of lock by the PLL. Each
condition may be optionally masked from affecting the RERR pin using the Receiver Error Mask Regis-
ter. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked
error occurs and goes low immediately when all unmasked errors go away
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Data Port (Input) - Audio data serial input pin.
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT
pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Data (Output) - Audio data serial output pin
Interrupt (Output) - Indicates errors and key events during the operation of the CS8427. All bits affecting
INT may be unmasked through bits in the control registers. The condition(s) that initiated interrupt are
readable through a control register. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero
User Data (Output) -
transmitter, see Figure 15 on page 23 for timing information. Alternatively, the U pin may be
set to output User data from the AES3 receiver, see
tion. If not driven, a 47 kΩ pull-down resistor is recommended for the U pin, since the default
state of the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the
transmitted user data will be zero. If the U pin is always set to be an output, thereby causing
the U bit manager to be the source of the U data, then the resistor is not necessary. The U pin
should not be tied directly to ground, in case it is programmed to be an output, and subse-
quently tries to output a logic high. This situation may affect the long term reliability of the
device. If the U pin is driven by a logic level output, then a 100 Ω series resistor is recom-
mended.
System Clock (Input) - When the OMCK System Clock Mode is enabled by the SWCLK bit in the Con-
trol 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as reference sig-
nal for OMCK/RMCK ratio expressed in register0x1E.
Digital Ground (Input) - Ground for the digital section. DGND should be connected to the same ground
as AGND
Positive Digital Power (Input) - Typically +3 to +5 V.
Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the
CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U
data access is primarily through the control port, using a microcontroller. Hardware mode provides an
alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be
permanently tied to VL+ or DGND
Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the CS8427 is in
the reset state.
Address Bit 1 (Two-Wire) / Serial Control Data in (SPI) (Input) - In Two-Wire mode, AD1 is a chip
address pin. In SPI mode, CDIN is the input data line for the control port interface
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8427. In Two-Wire mode, SCL requires an external pull-up resistor to VL+
May optionally be used to input User bit data for transmission by the AES3
Figure 15 on page 23
.
for timing informa-
CS8427
41