CS8427 Cirrus Logic, CS8427 Datasheet - Page 32

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

SISF - ISCLK frequency (for master mode)
SIRES1:0 - Resolution of the input data, for right-justified formats
SIJUST - Justification of SDIN data relative to ILRCK
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
SISPOL - ISCLK clock polarity
SILRPOL - ILRCK clock polarity
12.6 Serial Audio Output Port Data Format (6h)
SOMS - Master/Slave Mode Selector
SOSF - OSCLK frequency (for master mode)
SORES1:0 - Resolution of the output data on SDOUT and on the AES3 output
32
SOMS
7
Default = ‘0’
0 - 64 * Fsi
1 - 128 * Fsi
Default = ‘00’
00 - 24 bit resolution
01 - 20 bit resolution
10 - 16 bit resolution
11 - Reserved
Default = ‘0’
0 - Left-justified
1 - Right-justified
Default = ‘0’
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge
Default = ‘0’
0 - SDIN sampled on rising edges of ISCLK
1 - SDIN sampled on falling edges of ISCLK
Default = ‘0’
0 - SDIN data is for the left channel when ILRCK is high
1 - SDIN data is for the right channel when ILRCK is high
Default = ‘0’
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
Default = ‘0’
0 - 64 * Fso
1 - 128 * Fso
Default = ‘00’
SOSF
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and
00 - 24-bit resolution
6
of the block start, SDOUT pin only, serial audio output port clock must be derived
from the AES3 receiver recovered clock)
V bits, the time slot normally occupied by the P bit is used to indicate the location
SORES1
5
SORES0
4
SOJUST
3
SODEL
2
SOSPOL
1
CS8427
DS477PP3
SOLRPOL
0