CS8427 Cirrus Logic, CS8427 Datasheet - Page 40

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

13. PIN DESCRIPTION - SOFTWARE MODE
40
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
10
1
2
3
4
5
6
7
8
9
Serial Control Data I/O (Two-Wire) / Data Out (SPI) (Input/Output) - In Two-Wire mode, SDA is the con-
trol I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode,
CDOUT is the output data from the control port interface on the CS8427
Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input/Output) - A falling edge on this pin
puts the CS8427 into SPI control port mode. With no falling edge, the CS8427 defaults to Two-Wire
mode. In Two-Wire mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port
interface on the CS8427
Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-
emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-
emphasis other than 50/15 µs. This is also a start-up option pin, and requires a 47kΩ resistor to either
VL+ or DGND, which determines the AD2 address bit for the control port in Two-Wire mode
Differential Line Receiver (Input) - Receives differential AES3 data.
Positive Analog Power (Input) - Positive supply for the chip’s analog section. Nominally +5 V. This sup-
ply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock
Analog Ground (Input) - Ground for the analog section. AGND should be connected to the same ground
as DGND
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. Recom-
mended schematic and component values are given in
respectively. Application note AN159 provides additional resources for the PLL.
Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in hardware mode with multiple CS8427 devices where
synchronization between devices is important
Input Section Recovered Master Clock (Input/Output) - Input section recovered master clock output
when PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. When the
PLL is bypassed by the RXD0 bit in the Clock Source Control register, an external clock of 256 Fs may
be applied to this pin
SDA/CDOUT
* Pins which remain the same function in all modes.
+ Pins which require a pull up or pull down resistor
AD0/CS
to select the desired startup option.
ILRCK
RMCK
ISCLK
AGND
EMPH
RERR
SDIN
RXN
RXP
FILT
RST
VA+
1
2
3+
4*
5*
6*
7*
8*
9*
10*
11*
12*
13*
14*
*26
*25
*24
*23
*22
*18
*17
*16
*15
28
27
21
20
19
SCL/CCLK
AD1/CDIN
TXP
TXN
H/S
V +
DGND
OMCK
U
INT
SDOUT
OLRCK
OSCLK
TCBL
L
Figure 5 on page 10
and
Table 1 on page
CS8427
DS477PP3
18,