CS8427 Cirrus Logic, CS8427 Datasheet - Page 19

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

9. AES3 TRANSMITTER
The AES3 transmitter encodes and transmits audio
and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
Audio and control data are multiplexed together
and bi-phase mark encoded. The resulting bit
stream is driven to an output connector either di-
rectly or through a transformer.
The transmitter clock may be derived from the
clock input pin OMCK, or from the incoming data.
If OMCK is asynchronous to the data source, an in-
terrupt bit (TSLIP) is provided that will go high ev-
ery time a data sample is dropped or repeated. Be
aware that the pattern of slips does not have hyster-
esis and so the occurrence of the interrupt condition
is not deterministic.
The channel status (C) and user channel (U) bits in
the transmitted data stream are taken from storage
areas within the CS8427. The user can manually
access the internal storage or configure the CS8427
to run in one of several automatic modes. The Ap-
pendix: Channel Status and User Data Buffer Man-
agement provides detailed descriptions of each
automatic mode and describes methods of manual-
ly accessing the storage areas. The transmitted user
data can optionally be input through the U pin, un-
der the control of a control port register bit.
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data through the U pin.
9.0.1
The TCBL pin is used to control or indicate the
start of transmitted channel status block boundaries
and may be used as an input or output.
In some applications, it may be necessary to control
the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in three ways:
DS477PP3
shows the timing requirements for clocking U
Transmitted Frame and Channel
Status Boundary Timing
Figure
a) With TCBL set to input, driving TCBL high for
>3 OMCK clocks will cause a frame start, as well
as a new channel status block start.
b) If the AES3 output comes from the AES3 input,
setting TCBL as output will cause AES3 output
frame boundaries to align with AES3 input frame
boundaries.
c) If the AES3 output comes from the serial audio
input port while the port is in slave mode and
TCBL is set to output, the start of the A channel
sub-frame will be aligned with the leading edge of
ILRCK.
9.0.2
The line drivers are low skew, low impedance, dif-
ferential outputs capable of driving cables directly.
Both drivers are set to ground during reset (RST =
low), when no AES3 transmit clock is provided,
and optionally under the control of a register bit.
The CS8427 also allows immediate mute of the
AES3 transmitter audio data through a control reg-
ister bit.
External components are used to terminate and iso-
late the external cable from the CS8427. These
components are detailed in
AES3/SPDIF/IEC60958 Transmitter and Receiver
Components” on page
9.1 Mono Mode Operation
An AES3 stream may be used in more than one
way to transmit 96 kHz sample rate data. One
method is to double the frame rate of the current
format. This results in a stereo signal with a sample
rate of 96 kHz, carried over a single twisted pair ca-
ble. An alternate method is implemented using the
two sub-frames in a 48 kHz frame rate AES3 signal
to carry consecutive samples of a mono signal, re-
sulting in a 96 kHz sample rate stream. This allows
older equipment, whose AES3 transmitters and re-
ceivers are not rated for 96 kHz frame rate opera-
tion, to handle 96 kHz sample rate information. In
this “mono mode”, two AES3 cables are needed for
TXN and TXP Drivers
50.
“Appendix A: External
CS8427
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