CS8427 Cirrus Logic, CS8427 Datasheet - Page 44

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

15. PIN DESCRIPTION - HARDWARE MODE
44
COPY
DGND2
DGND
EMPH/U
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
ILRCK
ISCLK
SDIN
22
10
11
12
13
14
1
2
3
4
5
6
7
8
9
COPY Channel Status Bit (Output) - Reflects the state of the Copyright Channel Status bit in the incom-
ing AES3 data stream. If the category code is set to General, copyright will be indicated whatever the
state of the Copyright bit. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
Digital Ground (Input) - Ground for the digital section. DGND should be connected to the same ground
as AGND.
Pre-Emphasis Indicator / U-bit (Input/Output) - The EMPH/U pin either reflects the state of the EMPH
channel status bit in the incoming AES3 data stream, or is the serial U-bit input for the AES3 transmitted
data, clocked by OLRCK. If indicating emphasis: EMPH/U is low when the incoming Channel Status data
indicates 50/15 µs pre-emphasis. EMPH/U is high when the Channel Status data indicates no pre-
emphasis or indicates pre-emphasis other than 50/15 µs.
Differential Line Receiver (Input) - Receives differential AES3 data.
Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5V. This supply
should be as quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock
Analog Ground (Input) - Ground for the analog section. AGND should be connected to the same ground
as DGND
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. Recom-
mended schematic and component values are given in
respectively. Application note AN159 provides information about the PLL.
Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in hardware mode with multiple CS8427 devices where
synchronization between devices is important
Input Section Recovered Master Clock (Input/Output) - Input section recovered master clock output
when PLL is used. Frequency is 256x the sample rate (Fs).
Receiver Error (Output) - When high, indicates an error in the operation of the AES3 receiver. The sta-
tus of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to
go high are: parity error, bi-phase coding error, confidence, as well as loss of lock by the PLL.
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Data Port (Input) - Audio data serial input pin.
* Pins which remain the same function in all modes.
+ Pins which require a pull up or pull down resistor
EMPH/U
to select the desired startup option.
DGND2
ILRCK
RMCK
ISCLK
AGND
COPY
RERR
SDIN
RXN
RXP
FILT
RST
VA+
1+
2
3
4*
5*
6*
7*
8*
9*
10*+
11*+
12*
13*
14*
+*18
+28
*26
*25
*24
*23
*22
*17
*16
*15
27
21
20
19
ORIG
V 2+
TXP
TXN
H/S
V +
DGND
APMS
PRO/C
AUDIO/V
SDOUT
OLRCK
OSCLK
TCBL
L
L
Figure 5 on page 10
and
Table 1 on page
CS8427
DS477PP3
18,