CS8427 Cirrus Logic, CS8427 Datasheet - Page 39

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

12.19 OMCK/RMCK Ratio (1Eh) (Read Only)
This register allows the calculation of the incoming sample rate by the host micro-controller from the equation
SRR=Fso / Fsi. The Fso is determined by OMCK. This value is represented as an integer and a fractional part. The
value is meaningful only after the both the PLL has reached lock. F
256 Fso and OMCK is 12.288 MHz, Fso would be 48KHz(48 KHz=12.288 MHz / 256). Then if the in put
sample rate is also 48 KHz, you would get 1.0 from the SRR register.(The value from the SRR register is
hexadecimal, so the actual value you will get is 40h)
ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6]))
ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)
12.20 C-bit or U-bit Data Buffer (20h - 37h)
Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible
using these register addresses.
12.21 CS8427 I.D. and Version Register (7Fh) (Read Only)
ID3:0 - ID code for the CS8427. Permanently set to 0111
VER3:0 - CS8427 revision level. Revision A is coded as 0001
DS477PP3
ORR7
ID3
7
7
ORR6
ID2
6
6
ORR5
ID1
5
5
ORR4
ID0
4
4
ORR3
VER3
3
3
or example, if you set the CLK[1:0] bits to
ORR2
VER2
2
2
ORR1
VER1
1
1
CS8427
ORR0
VER0
0
0
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