CS8427 Cirrus Logic, CS8427 Datasheet - Page 23

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

DS477PP3
VLRCK
U
Output
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
U transitions are aligned within 1% of VLRCK period to VLRCK edges
In or Out
TCBL
VLRCK
U
SDIN
Input
Input
TXP(N)
TXP(N)
Output
TXP(N)
Output
VLRCK
VLRCK is a virtual word clock, which may not exist, is used to illustrate the CUV timing.
VLRCK duty cycle is 50%.
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.
VLRCK= ILRCK
VLRCK= ILRCK
If the serial audio input port is on slave mode and TCBL is an output, then VLRCK=ILRCK if SILRPOL=0 and
If the serial audio input port is in master mode and TCBL is an input, then VLRCK=ILRCK if SILRPOL=0 and
Figure 16. AES3 Transmitter Timing for C, U and V pin input data
Tth
Tth
* Assume MMTLR = 0
* Assume MMTLR = 1
Z
Z
Z
Figure 15. AES3 Receiver Timing for U pin output data
Data [4]
Data [4]
Tsetup
Data [0]
if SILRPOL =1.
if SILRPOL =1.
VCU[0]
Data [1]*
Data [0]*
±
Y
Thold
Data [5]
Data [1]
Data [5]
AES3 Transmitter in Mono Mode
AES3 Transmitter in Stereo Mode
VCU[1]
U[0]
Y
X
Y
Data [6]
Data [6]
Data [2]
Data [3]*
Data [2]*
VCU[2]
Y
Data [7]
Data [7]
Data [3]
Tsetup => 7.5% AES3 frame time
Tsetup => 15% AES3 frame time
VCU[3]
Thold = 0
Tth > 3OMCK if TCBL is Input
Thold = 0
Tth > 3OMCK if TCBL is Input
U[2]
X
X
X
Data [8]
Data [8]
Data [4]
Data [5]*
Data [4]*
VCU[4]
CS8427
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