CS8427 Cirrus Logic, CS8427 Datasheet - Page 29

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

12. CONTROL PORT REGISTER BIT DEFINITIONS
12.1 Control 1 (1h)
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
VSET - Transmitted Validity bit level
MUTESAO - Mute control for the serial audio output port
MUTEAES - Mute control for the AES transmitter output
INT1:INT0 - Interrupt output pin (INT) control
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
12.2 Control 2 (2h)
HOLD1:HOLD0 - Determine how received audio sample is affected when a receiver error occurs
RMCKF - Select recovered master clock output pin frequency.
MMR - Select AES3 receiver mono or stereo operation
DS477PP3
SWCLK
7
7
0
Default = ‘0’
0 - RMCK default function
1 - OMCK output on RMCK pin
Default = ‘0’
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
Default = ‘0’
0 - Not Muted
1 - Muted
Default = ‘0’
0 - Not Muted
1 - Muted
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull up resistor on the INT pin.
11 - Reserved
Default = ‘0’
0 - TCBL is an input
1 - TCBL is an output
Default = ‘00’
00 - Hold the last valid audio sample
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
Default = ‘0’
0 - RMCK is equal to 256 * Fsi
1 - RMCK is equal to 128 * Fsi
HOLD1
VSET
6
6
MUTESAO
HOLD0
5
5
MUTEAES
RMCKF
4
4
MMR
3
3
0
MMT
INT1
2
2
MMTCS
INT0
1
1
CS8427
MMTLR
TCBLD
0
0
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