CS8427 Cirrus Logic, CS8427 Datasheet - Page 27

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

ment bit in MAP allows successive reads or writes
of consecutive registers. Each byte is separated by
an acknowledge bit, ACK, which is output from the
CS8427 after each input byte is read. The ACK bit
is input to the CS8427 from the microcontroller af-
ter each transmitted byte. The Two-Wire Mode is
compatible with the I
10.3 Interrupts
The CS8427 has a comprehensive interrupt capa-
bility. The INT output pin is intended to drive the
interrupt input pin on the host microcontroller. The
INT pin may be set to be active low, active high, or
active low with no active pull-up transistor. This
DS477PP3
C C L K
CS
C D IN
C D O U T
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
0010000
C H IP
High Impedance
2
C protocol.
R/W
SDA
SCL
Note 1: AD2 is derived from a resistor attached to the EMPH pin,
Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP
Note 3: If operation is a read, the last bit of the read should be a NACK(high)
Figure 20. Control Port Timing in Two-Wire Mode
Start
M A P
Figure 19. Control Port Timing in SPI Mode
AD1 and AD0 are determined by the state of the corresponding pins
0010
MSB
b y te 1
AD2-0
DATA
Note 1
b y te n
R/W
LSB
ACK DATA7-0 ACK DATA7-0 ACK
last mode is used for active low, wired-OR hook-
ups with multiple peripherals connected to the mi-
crocontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off using mask register bits.
In addition, each source may be set to rising edge,
falling edge, or level sensitive. Combined with the
option of level sensitive or edge sensitive modes
within the microcontroller, many different set-ups
are possible depending on the needs of the equip-
ment designer.
A D D R E S S
C H IP
0010000
Note 2
R/W
MSB
Note 3
Stop
LSB MSB
CS8427
LSB
27