MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 101
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MT90520AG
Manufacturer Part Number
MT90520AG
Description
8-Port Primary Rate Circuit Emulation AAL1 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90520AG.pdf
(180 pages)
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Thus, the “carry” signal results in the desired clock rate (in this case, it is slightly greater than 1/2 the line rate
clock).
After the gapping circuitry, the resulting clock (carry) is divided by 3000, which represents the number of payload
bits transmitted within one RTS period (7 cells containing 47 payload bytes, and one cell containing 46 payload
bytes). As with UDT operation, every time RTS_CLK pulses, the current value of the fnxi counter is stored in a
FIFO. A value from the FIFO is transmitted to the TX_SAR cell header generator circuit every 8-cell sequence.
Note: Because of the divide-by-3000 circuitry, the TX SRTS circuitry won’t work when a VC is set up for the SDT w/
CAS mode of operation. The problem is caused by the fact that there aren’t necessarily 3000 TDM payload bits in
an 8-cell cycle in these operational modes. Therefore, RTS nibble generation and SRTS clock recovery are only
supported in “basic” SDT operation.
4.7.2.5
The receive SRTS circuit sub-module generates a bit-rate clock based on RTS values extracted from the headers
of ATM cells received on the UTOPIA bus.
As outlined in U.S. Patent No. 5,260,978, the receive SRTS circuit generates a recovered clock based on a
comparison between the incoming RTS values and the network clock, fnxi. This comparison provides enough
information to re-create the remote (transmit) clock at the local end.
The Receive SRTS circuitry is quite simple, consisting only of a FIFO and a digital PLL, as seen in Figure 41. In
addition, the Receive SRTS circuit makes use of signals generated within the Transmit SRTS circuitry, explained in
Section 4.7.2.4. These pre-generated signals are also shown in Figure 41.
Receive SRTS Circuit Sub-Module
Table 19 - Sample Gapping Circuitry Calculation (N = 18)
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
...
N
accumulator
output
Zarlink Semiconductor Inc.
18
22
26
12
30
16
20
24
10
28
14
...
0
4
8
2
6
0
MT90520
101
accumulator
input
18
22
26
12
30
16
20
24
10
28
14
18
...
4
8
2
6
0
carry
...
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
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