MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 94

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Section 4.7.2.2, “Synchronous Clocking Circuit” may be sourced from the internal PLL clock or the TDM input clock
for any DS1/E1 port of the device.
Note1: Shaded sections of figure above indicate circuitry outlined elsewhere in this document.
Note2: The SDT/UDT interface is replicated on a per-port basis. The backplane interface and common clock generation circuitry are only implemented once
per device.
External
. . .
16:2
Mux
PLL
Figure 34 - Interface to TDM Bus Module and Common Clock Generation Circuitry
PLLCLK
PLL_INPUT_SEL
Generation (one
Common Clock
Interface and
TDM_CLK
per device)
Backplane
PRI_REF
Digital PLL
Mux
4:1
EXT/INT
Mux
C4M_C2M_
2:1
Adaptive Mode
8 kHz Network Mode
SRTS Mode
Line Clocking Mode
in
Zarlink Semiconductor Inc.
SLV/MSTR
Mux
2:1
MT90520
C4M_C2M_
94
out
F0_MODE
<1:0>
common TDM rate clock
MCLK/2
/512 or /256
Convert to
SDT/UDT Interface (one
External
Format
F0_out
per port)
F0_in
F0_MODE<2>
Mux
CLKSEL
4:1
SLV/MSTR
Mux
2:1
C4M/C2M
F0
STiCLK
LOS
SToCLK
Data Sheet
Module
TDM
Bus