MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 19

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.0
3.1
Ball pin numbers are given in the following tables as defined in Figure 3.2.3 on page 34. Pins for buses are listed
with the MSB appearing first.
I/O definitions are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND).
Input pad types are: CMOS or Schmitt, 3.3 V. The notations “PU” and “PD” are used, respectively, to indicate that a
pad has a weak internal pullup or pulldown resistor. All 3.3 V inputs are 5 V tolerant. The 3.3 V CMOS inputs have
a switching threshold of 1.6 V, and tolerate input levels of up to 5 V; therefore they are 5 V TTL compatible.
Output pad types are described by voltage rail and current capability. 3.3 V CMOS outputs will satisfy 5 V TTL input
thresholds at the rated current of the output.
D10, C9, B9, A9,
D9, C8, B8, A8,
D15, B16, C16,
C18, D17, A19,
B19, C19, D18,
C15, A16, E15,
A17, B17, D16,
C17, A18, B18,
B10, A10, C11,
D11, E11, C10,
Ball Pin #
A20, E17
B11, D12
Functional Pin Descriptions
Pin Descriptions
C12
A11
D8
C7
E9
A7
B7
CPU_ADD[20:1
CPU_DATA[15:
RDY/DTACK
Pin Name
Intel/Moto
WR/R_W
RD/DS
AEM
IRQ
CS
0]
]
Table 1 - Microprocessor Interface Pins
I/O
I/O
O
O
I
I
I
I
I
I
CMOS PD /
CMOS PD
CMOS PU
CMOS PU
CMOS PU
CMOS PD
CMOS PD
12 mA
24 mA
24 mA
3.3 V,
3.3 V,
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Type
Zarlink Semiconductor Inc.
MT90520
This input selects the microprocessor interface mode as
Intel (pulled HIGH) or Motorola (pulled LOW). This pin
must be configured before power-up.
Active LOW chip select signal.
Active LOW Write Strobe (Intel) / Read_Write (Motorola).
Active LOW Read Strobe (Intel) / Active LOW Data Strobe
(Motorola).
Access External Memory - CPU accesses external
memory when HIGH (internal memory and registers when
LOW). This pin is usually connected to a high-order CPU
address line.
CPU Address lines A20-A1.
All microprocessor accesses to the device are word-wide,
but addresses in this document are given as byte
addresses. The virtual A[0] bit would select between high
and low bytes within a word.
CPU data bus. All CPU accesses are word accesses.
Ready (Intel) / Data Transfer Acknowledge (Motorola).
Acts as normal output in Intel mode, tristated when CS is
HIGH; acts as active LOW pseudo-open-drain output in
Motorola mode.
Active LOW interrupt line (operates as open-drain: high-
impedance when inactive).
19
Description
Data Sheet