MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 130

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.6
Address: 3000 (Hex)
Label: MTCR
Reset Value: 09C4 (Hex)
Address: 3002 (Hex)
Label: MTSR1
Reset Value: 0000 (Hex)
STATUS_0
STATUS_1
STATUS_2
STATUS_3
STATUS_4
STATUS_5
STATUS_6
STATUS_7
_PERIOD
Reserved
CUT_VC
Label
Label
Reassembly-Side Timeout Module
Position
Position
15:0
15:8
Bit
Bit
0
1
2
3
4
5
6
7
Table 56 - MIB Timeout Configuration Register
Type
Type
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Table 57 - MIB Timeout Status Register
Reassembly Cell Loss Integration Period.
If cells on a VC are continuously lost for this period of time (given in ms), the
CUT_VC_STATUS bit is set in the Timeout Configuration Register (3200h + p*2h)
corresponding to the VC’s “VC TDM Port”. Default value = 2.5 s.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 0.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 1.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 2.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 3.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 4.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 5.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 6.
If set, indicates that either an unmasked late cell event or an unmasked cut VC event has
occurred on port 7.
Always reads “0000_0000”.
Zarlink Semiconductor Inc.
MT90520
130
Description
Description
Data Sheet