MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 64

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT90520
Data Sheet
A cell buffer empty event occurs whenever the Read Pointer equals the Write Pointer. This condition is cleared
when the Data TX_SAR is disabled or when the Write Pointer is changed.
If the Write Pointer is set to a value equal to or greater than the cell buffer size, the cells in the buffer will be sent
repetitively.
The Write Pointer should never be set to the same value as the Read Pointer when there are cells in the buffer
awaiting transmission or during transmission of the cell pointed to by the Read Pointer.
If the AUTO bit is set in the Data TX_SAR Control Register at 103Eh, the Data TX_SAR sends cells to the UTOPIA
module whenever the TX_SAR module is not busy transmitting CBR cells (i.e., either UDT- or SDT-formatted AAL1
cells). Contrarily, if the AUTO bit is not set, the Data TX_SAR sends out cells at a user-configurable data rate. The
user may configure the time between cell transmissions by programming the Data Cell Generation Time Out
Register at 1040h. Cells may be sent in time intervals from 1ms to 1s.
As mentioned above, the Data TX_SAR does not actually generate the cells to be transmitted. Rather, it simply
reads 54-byte cells (consisting of 5 bytes of header, 1 “filler” header byte (UDF2 field) required for the 16-bit
UTOPIA bus, and 48 bytes of payload) directly from a location in external memory which is identified by a Data
TX_SAR Cell Buffer base address and the Read Pointer. The base address of the buffer is user-programmable, as
is the number of cells that can be stored in the buffer. The user can select (via the register at byte address 1038h) a
buffer capable of holding 16, 32, 64, or 128 cells. Each cell is allocated 64 bytes in external memory. Cells written
into the Data TX_SAR Cell Buffer must conform to the format shown in Figure 25.
4.5.4.2
Error Handling
The Data TX_SAR has a single status bit to indicate whether the Data TX_SAR Cell Buffer in external memory is
empty (declared when the Data TX_SAR’s read pointer is equal to the write pointer controlled by the CPU). The
Transmit Cell Buffer Empty bit in the Data TX_SAR Status Register at 1042h can be enabled to cause an interrupt
to be generated on IRQ.
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