MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 170
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MT90520AG
Manufacturer Part Number
MT90520AG
Description
8-Port Primary Rate Circuit Emulation AAL1 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90520AG.pdf
(180 pages)
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Figure 68 below illustrates the connections from the external pins of the UTOPIA interface to a PHY device, when
the MT90520 is operating in ATM mode.
PHY Device
Note 1: The MT90520 does not have to drive the UTOPIA clock. The UTO_IN_CLK and UTO_OUT_CLK pins of the
MT90520 can either be inputs or outputs.
Note 2: When in ATM mode, UTO_IN_CLAVATM_ENBPHY, UTO_IN_SOC, UTO_OUT_CLAVATM_ENBPHY and
UTO_OUT_SOC should be pulled down. It is also recommended to pull up UTO_IN_ENBATM_CLAVPHY and
UTO_OUT_ENBATM_CLAVPHY.
RxData[15:0]
TxData[15:0]
RxEnb*
RxSOC
RxClav
TxEnb*
TxSOC
TxClav
RxPrty
TxPrty
Figure 68 - ATM Mode: External UTOPIA Pin Connections
RxClk
TxClk
UTO_OUT_CLK
UTO_OUT_ENBATM_CLAVPHY
UTO_OUT_CLAVATM_ENBPHY
UTO_OUT_DATA[15:0]
UTO_OUT_SOC
UTO_IN_CLK
UTO_IN_ENBATM_CLAVPHY
UTO_IN_CLAVATM_ENBPHY
UTO_IN_DATA[15:0]
UTO_IN_SOC
UTO_OUT_PAR
UTO_IN_PAR
Zarlink Semiconductor Inc.
MT90520
170
RX UTOPIA
TX UTOPIA
RX Parity
TX Parity
Interface
Interface
MT90520
Mode)
(ATM
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