MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 154

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

CPU_DATA[15:0
Address Setup - (R/W, AEM and
CPU_ADD[20:1] VALID) to (CS and DS
asserted)
Address Hold - (CS or DS de-asserted)
to (AEM, CPU_ADD[20:1] and R/W
INVALID)
DTACK High - CS asserted to DTACK
driven high
DTACK Delay - (CS and DS asserted)
to DTACK asserted
DTACK High-Impedance - CS de-
asserted to DTACK high-impedance
Data Input Setup - CPU_DATA[15:0]
VALID to (CS and DS asserted)
Data Input Hold - (CS or DS de-
asserted) to CPU_DATA[15:0] INVALID
Note 1: MCLK = 66 MHz (15.2 ns)
Note 2: Both CS and DS must be asserted for a write cycle to occur. A write cycle is completed when either CS or DS is de-asserted.
Note 3: There should be a minimum of 3 MCLK periods between CPU accesses (CS de-asserted), to allow the MT90520 to recognize the
accesses as separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses).
CPU_ADD[20:1]
AEM
DTACK
R_W
CS
DS
Register access
Memory access
Characteristic
t
WDTKH
t
Table 91 - Motorola Microprocessor Interface Timing - Write Cycle Parameters
t
ADDS
DS
Figure 50 - Motorola CPU Interface Timing - Write Access
t
t
t
t
WDTKH
WDTKZ
Sym.
t
WACC
ADDS
ADDH
t
t
DH
DS
t
Zarlink Semiconductor Inc.
WACC
Min.
167
182
ADDRESS VALID
0
0
0
0
0
0
DATA VALID
MT90520
154
Typ.
197
Max.
2021
213
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ADDH
ADDH
C
C
11 MCLK < t
12 MCLK < t
C
L
L
L
= 75 pF
= 75 pF
= 75 pF
Test Conditions
t
DH
WACC
WACC
t
WDTKZ
< 14 MCLK
< 133 MCLK
Data Sheet
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT