HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 172

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
7–8
f
software can generate static timing analysis scripts for use in Synopsys
PrimeTime tools. In addition, timing can be further verified in
third-party, timing-driven simulation tools.
When software timing verification of the Stratix II prototype FPGA is
complete, you can verify your prototype in hardware. It is a requirement
of the HardCopy II design flow that you fully verify the Stratix II FPGA
prototype timing over the range of operating conditions that your design
is exposed to.
The next step is to create and compile your HardCopy II design revision.
By default, your HardCopy II compilation is run with the same timing
constraints used during the compilation and verification of your Stratix II
FPGA. If you wish to change the target timing specifications for the
HardCopy II revision, you can do so by changing the HardCopy II timing
constraints before compiling. When the HardCopy II compilation is
complete, just as you do after the Stratix II compilation, run TimeQuest or
Classic Timing Analyzer to check timing results. You should review and
resolve any timing failures that are reported.
One of the final steps in the HardCopy II design flow in the Quartus II
software is the revision comparison check. Part of this check compares
timing constraints and settings between the Stratix II and HardCopy II
revisions of the project. Any differences between the two are reported. If
you change the timing constraints after completing Stratix II FPGA
prototyping, the Revision Compare tool will report the change and you
will be asked to waive this difference in the design review.
When your Quartus II design is transferred to the HCDC, it includes an
industry-standard (SDC) version of the HardCopy II timing constraints.
This version is the set of legal timing constraints for the design that
include commands only from the sdc package in the Quartus II software.
For the HardCopy II design flow, you may not use any commands except
those in the sdc package in the Quartus II software. In addition, you must
correct all timing constraints that generate warning messages in the
Quartus II software.
For more detailed information on the Quartus II sdc package, refer to the
sdc package section in the Tcl Packages and Commands chapter of the
Quartus II Scripting Reference Manual.
Using the TimeQuest Timing Analyzer
The TimeQuest timing analyzer plays an integral part in the Quartus II
HardCopy II timing closure flow, from the specification of timing
constraints to the verification of design requirements.
Altera Corporation
September 2008