HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 79

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
(4)
(5)
Output t
Output t
t
DPA run length
DPA jitter tolerance
(peak-to-peak)
DPA lock time
f
f
DUTY
HSCLK
HSCLK
Table 4–40. HardCopy II High-Speed I/O Specifications for HC210W Device
Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices
Note (1)
These numbers are preliminary and pending further silicon characterization.
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input
clock frequency × W ≤ 640.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not
have a minimum toggle rate.
Contact the Altera Applications Group for more information.
(clock frequency)
= f
RISE
FALL
Symbol
Table
Symbol
HSDR
(Part 1 of 2)
/ W
4–40:
Parallel Rapid I/O
W = 2 to 32 (LVDS, HyperTransport technology)
(2)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
Miscellaneous
Table 4–41
HC220, HC230 and HC240 HardCopy II devices.
Standard
SPI4
—
—
—
—
—
—
All differential I/O standards
All differential I/O standards
shows the high-speed I/O timing specifications for HC210,
Conditions
Conditions
0000000000
1111111111
10010000
10010000
10101010
10101010
Training
Pattern
—
—
—
—
Transition
Density
100%
10%
25%
50%
—
—
—
—
—
Min
Min
150
45
(5)
(5)
(5)
(5)
(5)
(5)
—
—
—
—
—
16
16
Notes
HighSpeed I/O Specifications
Typ
50
—
—
—
—
—
—
—
—
—
—
—
Typ
(1),
—
—
—
(2)
6,400
Max
Max
520
500
717
(5)
(5)
55
—
—
—
—
—
—
—
—
(Part 2 of 2)
Number of
repetitions
MHz
MHz
MHz
Unit
Unit
ps
ps
UI
UI
%
4–37